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| White Electronic Designs WV3EG6434S-BD4 ADVANCED* 256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL FEATURES DDR266 and DDR333 Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power supply: 2.5V 0.20V Standard 200 pin SO-DIMM package * Package height options: BD4: 31.75mm (1.25") NOTE: Consult factory for availability of: * Lead-Free or RoHS Products * Vendor source control options * Industrial temperature option * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. DESCRIPTION The WV3EG6434S is a 32Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM component. The module consists of eight 32Mx8 DDR SDRAMs in BGA package mounted on a 200 Pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. OPERATING FREQUENCIES DDR333 @CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN CONFIGURATIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VREF VREF VSS VSS DQ0 DQ4 DQ1 DQ5 VCC VCC DQS0 DM0 DQ2 DQ6 VSS VSS DQ3 DQ7 DQ8 DQ12 VCC VCC DQ9 DQ13 DQS1 DM1 VSS VSS DQ10 DQ14 DQ11 DQ15 VCC VCC CK0 VCC CK0# VSS VSS VSS DQ16 DQ20 DQ17 DQ21 VCC VCC DQS2 DM2 DQ18 DQ22 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol VSS VSS DQ19 DQ23 DQ24 DQ28 VCC VCC DQ25 DQ29 DQS3 DM3 VSS VSS DQ26 DQ30 DQ27 DQ31 VCC VCC NC NC NC NC VSS VSS *DQS8 *DM8 NC NC VCC VCC NC NC NC NC VSS VSS *CK2 VSS *CK2# VCC VCC VCC *CKE1 CKE0 NC NC A12 A11 Pin 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Symbol A9 A8 VSS VSS A7 A6 A5 A4 A3 A2 A1 A0 VCC VCC A10/AP BA1 BA0 RAS# WE# CAS# CS0 *CS1# NC NC VSS VSS DQ32 DQ36 DQ33 DQ37 VCC VCC DQS4 DM4 DQ34 DQ38 VSS VSS DQ35 DQ39 DQ40 DQ44 VCC VCC DQ41 DQ45 DQS5 DM5 VSS VSS Pin 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Symbol DQ42 DQ46 DQ43 DQ47 VCC VCC VCC *CK1# VSS *CK1 VSS VSS DQ48 DQ52 DQ49 DQ53 VCC VCC DQS6 DM6 DQ50 DQ54 VSS VSS DQ51 DQ55 DQ56 DQ60 VCC VCC DQ57 DQ61 DQS7 DM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VCC VCC SDA SA0 SCL SA1 VCCSPD SA2 NC NC WV3EG6434S-BD4 ADVANCED PIN NAMES A0 - A12 BA0-BA1 DQ0-DQ63 DQS0-DQS7 CK0 CK0# CKE0 CS0# RAS# CAS# WE# DM0-DM7 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock input Clock input Clock Enable Input Chip select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply Power Supply for DQS Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Identification Flag No Connect * These pins are not used in this module. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FUNCTIONAL BLOCK DIAGRAM S0# CKE0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S0# WV3EG6434S-BD4 ADVANCED DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S0# DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S1# DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S1# DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S0# DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S0# DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S1# DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S1# BA0 - BA1 A0 - A12 RAS# CAS# WE# BA0-BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: SDRAMs CAS#: SDRAMs WE#: SDRAMs Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA VCCSPD VCC/VCCQ SPD DDR SDRAM CK0 CK0# PLL DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM VREF VSS DDR SDRAM DDR SDRAM NOTE: All resistor values are 22 ohms unless otherwise specified. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. WV3EG6434S-BD4 ADVANCED Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -0.5 to 3.6 -1.0 to 3.6 -55 to +150 8 50 Units V V C W mA DC OPERATING CONDITIONS TA = 0C to 70C Parameter Supply voltage(for device with a nominal VCC of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage (system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK# inputs Input Differential Voltage, CK and CK# inputs Input crossing point voltage, CK and CK# inputs Input leakage current Output leakage current Output High Current(Normal strengh driver); VOUT = VTT + 0.84V Output High Current(Normal strengh driver); VOUT = VTT - 0.84V Output High Current(Half strengh driver); VOUT = VTT + 0.45V Output High Current(Half strengh driver); VOUT = VTT - 0.45V Symbol VCC VCCQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) II IOZ IOH IOL IOH IOL Min 2.3 2.3 VCCQ/2-50mV VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 1.15 -2 -5 -16.8 16.8 -9 9 Max 2.7 2.7 VCCQ/2+50mV VREF+0.04 VCCQ+0.3 VREF-0.15 VCCQ+0.3 VCCQ+0.6 1.35 2 5 Unit V V V V V V V V V uA uA mA mA mA mA Note 1 2 4 4 3 5 Notes: 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VCCQ of the transmitting device and must track variations in the dc level of the same. CAPACITANCE TA = 25C, f = 1MHz, VCC = 2.5V, VREF =2.5V 200mV Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#, CAS#, WE#) Input Capacitance (CKE0) Input Capacitance (CK0,CK0#) Input Capacitance (CS0#) Input Capacitance (DQM0-DQM8) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) April 2005 Rev. 0 4 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT Max 21 21 21 3 12 10 21 10 Unit pF pF pF pF pF pF pF pF White Electronic Designs Corp. reserves the right to change products or specifications without notice. White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG6434S-BD4 ADVANCED IDD SPECIFICATIONS AND TEST CONDITIONS Recommended operating conditions, 0C TA 70C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V DDR333@ CL=2.5 Parameter Operating Current Symbol Conditions IDD0 One device bank; Active - Precharge; tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-Read-Precharge; Burst = 2; tRC=tRC(MIN );tCK=tCK(MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power- down mode; tCK=tCK(MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. Vin = Vref for DQ, DQS and DM. CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with keeping >= VIH(min) or = < VIL(max); VIN = VREF for DQ, DQS and DM One device bank active; Power-down mode; tCK(MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continous burst; One device bank active;Address and control inputs changing once per clock cycle; tCK=tCK(MIN); Iout = 0mA. Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. tRC=tRC(MIN) CKE 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands. Max 720 DDR266@ CL=2 Max 640 DDR266@ CL=2.5 Max 640 Units mA 920 840 840 mA Operating Current Precharge Power-Down Standby Current Idle Standby Current IDD1 IDD2P 24 240 24 200 24 200 mA mA IDD2F 200 185 185 mA Precharge Quiet Standby Current Active Power-Down Standby Current IDD2Q IDD3P 280 440 240 360 240 360 mA mA Active Standby Current IDD3N 1280 1120 1120 mA Operating Current IDD4R 1280 1080 1080 mA Operating Current IDD4W Auto Refresh Current Self Refresh Current Operating Current IDD5 IDD6 IDD7A 1360 24 2240 1280 24 2080 1280 24 2080 mA mA mA Note: IDD speicification is based on Samsung components. Other DRAM manufacturers specification may be different. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG6434S-BD4 ADVANCED DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT : ONE BANK 1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst * IDD7A : OPERATING CURRENT : FOUR BANKS 1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst 4. 4. * * * * * Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3 White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG6434S-BD4 ADVANCED DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS 0C TA 70C, VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time CL=2.0 CL=2.5 Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSLMR 335 Min 60 72 42 18 18 12 15 1 1 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 -0.7 -0.7 0.5 0.5 1.0 0.67 Max Min 65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 262 Max Min 65 75 45 20 20 15 15 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 265 Max Unit ns ns ns ns ns ns ns tCK tCK ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns V/ns V/ns V/ns Note 70K 120K 120K Clock high level width Clock low level width DQS-out access time from CK/CK# Output data access time from CK/CK# Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time (fast) Address and Control Input hold time (fast) Address and Control Input setup time (slow) Address and Control Input hold time (slow) Data-out high impedence time from CK/CK# Data-out low impedence time from CK/CK# Input Slew Rate (for input only pins) Input Slew Rate (for I/O pins) Output Slew Rate (x4,x8) Output Slew Rate Matching Ratio (rise to fall) 12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 5 5 5 2 1.1 1.1 1.1 6 6 6 6 +0.7 +0.7 +0.75 +0.75 +0.75 +0.75 6 7 4.5 1.5 4.5 1.5 4.5 1.5 Note: AC Timing Parameters are based on Samsung components. Other DRAM Manufacturers parameters may be different. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG6434S-BD4 ADVANCED DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) 0C TA 70C, VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V Parameter Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time 1. 2. 3. 4. 5. 6. Symbol tMRD tDS tDH tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP tDAL 335 Min 12 0.45 0.45 2.2 1.75 6 75 200 7.8 tHP-tQHS tCLmin or tCHmin 0.4 18 (tWR/tCK) + (tRP/tCK) Max Min 15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP-tQHS tCLmin or tCHmin 262 Max Min 15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP-tQHS tCLmin or tCHmin 265 Max Unit ns ns ns ns ns ns ns tCK us ns ns ns tCK Note 7 7 4 1 5 -- -- 0.55 0.6 -- -- 0.75 0.6 -- -- 0.75 0.6 0.4 20 (tWR/tCK) + (tRP/tCK) 0.4 20 (tWR/tCK) + (tRP/tCK) 3 tCK Maximum burst refresh cycle : 8 The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. A write command can be applied with tRCD satisfied after this command. For registered DIMMs, tCL and tCH are >_ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tIS (ps) 0 +50 +100 tIH (ps) 0 +50 +100 This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tDS (ps) 0 +75 +150 tDH (ps) 0 +75 +150 This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ORDERING INFORMATION FOR BD4 Part Number WV3EG6434S335BD4 WV3EG6434S262BD4 WV3EG6434S265BD4 Speed 166MHz/333Mb/s 133MHz/266Mb/s 133MHz/266Mb/s CAS Latency 2.5 2 2.5 tRCD 3 2 3 WV3EG6434S-BD4 ADVANCED tRP 3 2 3 Height* 31.75 (1.25") 31.75 (1.25") 31.75 (1.25") NOTES: * Consult Factory for availability of Lead-Free or RoHS products. (F = Lead-Free, G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option PACKAGE DIMENSIONS FOR BD4 67.56 (2.66) 63.60 (2.50) Full R 2X 2.54 (0 .100) MAX. 4.00 0.10 (0.16 0.039) 20.00 (0.79) 1 39 41 199 31.75 (1.25) 6.00 (0.24) 2.15 (0.086) 11.40 (0.456) 4.20 (0.17) 2.40 (0.096) 47.40 (1.896) 2- 1.80 (0.07) 3.98 (0.157) MIN. 1.0 0.1 (0.039 0.004) 1.80 (0.07) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) TOLERANCES: 0.15 (0.006) UNLESS OTHERWISE SPECIFIED White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title 256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL WV3EG6434S-BD4 ADVANCED Revision History Rev # Rev 0 History Created Release Date 4-05 Status Advanced White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 0 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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